1. Technical Field
This disclosure relates to a DC-DC (direct current to direct-current) converter that controls operations of a switching element based on an output voltage and maintains the output voltage within a predetermined range.
More particularly, the disclosure relates to a DC-DC converter that supplies operational power to various types of semiconductor integrated circuit (IC) devices, such as a central processing unit (CPU) and a memory (RAM, ROM, etc.), mounted on any of various types of electronic apparatuses. For example, applications thereof can be a power source for digital home appliance such as DVD players using both blue- and red-type LD, and DVD-ROM/R/RW using both blue- and red-type LD for notebook PCs and desktop PCs.
2. Discussion of the Background
These days, as typified by cell phones, small mobile devices are considerably popular, and secondary batteries are used as a power supply for such small mobile device. Further, the above-described electronic apparatuses include a great number of ICs, and these ICs require power respective supply. The power supply required for operations of a load is generated in a DC-DC converter. If the power supply becomes unstable, operations of the load become unstable, and accordingly, malfunction will occur. Therefore, the DC-DC converter needs to generate a stable voltage as the power supply consistently.
FIG. 8 shows circuitry of a known DC-DC converter 201. The DC-DC converter 201 includes a control circuit 202 formed on a one-chip IC device, and multiple external elements. A signal SG1 output from the control circuit 202 is supplied to a gate of an output transistor 203 that is an enhanced N-channel MOS (negative channel metal oxide semiconductor) transistor.
A supply voltage input terminal VIN is connected to one terminal of a coil 204 for increasing voltage, and the other terminal of the coil 204 is connected to a drain of the output transistor 203. A source of the output transistor 203 is connected to ground (GND). Additionally, a diode 205 is connected between the drain and the source of the output transistor 203. More specifically, an anode of the diode 205 is connected to the source of the transistor 203, and a cathode of the diode 205 is connected to the drain of the transistor 203.
A junction node between the coil 204 and the output transistor 203 is connected to an anode of a diode 206, and a cathode of the diode 206 is connected to an output terminal 208. The output terminal 208 is connected to ground GND via a smoothing capacitor 207. In other words, a smoothing circuit formed by both the smoothing capacitor 207 and the coil 204 smoothes an output voltage VOUT. Further, the output terminal 208 is connected to the control circuit 202, and the output voltage VOUT is provided to the control circuit 202.
The control circuit 202 includes an error amplification circuit 211, a reference-voltage generation circuit 215, a PWM (Pulse Width Modulation) comparison circuit 212, a triangular-wave generation circuit 213, and an output control circuit 214.
The error amplification circuit 211 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplification circuit 211 receives a voltage VDIV generated by dividing the output voltage VOUT from the output terminal 208 by feedback resistors 216 and 217. The non-inverting input terminal of the error amplification circuit 211 receives a reference voltage VREF from the reference-voltage generation circuit 215.
In the error amplification circuit 211, a series circuit, not shown, that includes a phase compensating capacitor and a resistor is connected between the output terminal of the error amplification circuit 211 and the inverting input terminal, thereby preventing oscillation of the error amplification circuit 211.
The error amplification circuit 211 compares the reference voltage VREF with the voltage VDIV that is generated by dividing output voltage VOUT by feedback resistors 216 and 217 with the reference voltage VREF. Therefore, the error amplification circuit 211 generates an error output signal SG2 by amplifying differences between the voltage VDIV and VREF, and outputs the error output signal SG2 to the PWM comparison circuit 212, in a subsequent stage.
The PWM comparison circuit 212 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The non-inverting input terminal of the PWM comparison circuit 212 receives the error output signal SG2 from the error amplification circuit 211, and the inverting input terminal of the PWM comparison circuit 212 receives a triangular wave signal SG3 from the triangular-wave generation circuit 213. The PWM comparison circuit 212 compares the error output signal SG2 and the triangular wave signal SG3.
The PWM comparison circuit 212 outputs a pulse signal to the output control circuit 214 as a duty control signal SG4 that turns low when the triangular wave signal SG3 has a voltage higher than the error output signal SG2, and turns high when the triangular wave signal SG3 has a voltage equal to or smaller than the error output signal SG2.
The output control circuit 214 outputs to the gate of the output transistor 203 the duty control signal SG4 from the PWM comparison circuit 212, as above-described output signal SG1.
The DC-DC converter 201 having the configuration described above switches the output transistor 203 between on and off based on the output signal SG1 output from the control circuit 202, thereby keeping the output voltage VOUT at a predetermined voltage value.
When the output voltage decreases, the level of the error output signal SG2 of the error amplification circuit 211 rises. On the other hand, when the output voltage increases, the level of the error output signal SG2 of the error amplification circuit 211 declines.
In the PWM comparison circuit 212, when the level of the error output signal SG2 rises, the period during which the level of the triangular wave signal SG3 is higher than that of the error output signal SG2 is shorter, therefore, a period during which the duty control signal SG4 is high (hereinafter “high level signal period”) becomes longer. That is, a duty ratio of signal SG4 increases.
By contrast, in the PWM comparison circuit 212, when the level of the error output signal SG2 declines, the period during which the signal level of the triangular wave signal SG3 is higher than that of the error output signal SG2 is longer, therefore, the high level signal period of the duty control signal SG4 becomes shorter. That is, the duty ratio of signal SG4 decreases.
Further, as shown in FIG. 9B, when a slope of the triangular wave output from the triangular-wave generation circuit 213 shows an identical linearity, it is possible to obtain the stable output voltage by feedback of the output voltage VOUT. However, actually, as shown in FIGS. 9A and 9B, the slope of the triangular wave is a non-linear. Due to the non-linearity of the slope, the pulse width of a subsequent duty control signal from the PWM comparison circuit 212 fluctuates, which is a problem.
For example, as shown in FIG. 9A, when the output voltage VOUT is high, the DC-DC converter needs to reduce the pulse width, and therefore, the level of the error output signal SG2 is lowered. After one clock (CLK), the level of the error output signal SG2 is lowered, and at a non-linear part of the slope of the triangular wave, the pulse width becomes shorter than that for the identical linearity shown in FIG. 9B.
By contrast, when the triangular wave has the slope shapes shown in FIG. 9C, the pulse width expands to become greater than that for the identical linearity shown in FIG. 9B.
As described above, since the output triangle slope has such a non-linear shape, it can take a longer time to converge on a required voltage, and at worst, the DC-DC converter can fail to generate the required output voltage.
Several approaches have been tried in an attempt to make the DC-DC converter generate a stable voltage consistently.
In one known configuration of the DC-DC converter, when an output voltage is lower than a predetermined voltage that is offset from a reference voltage, an output transistor is turned on while a duty control signal has a maximum duty ratio by comparing an error output signal and a triangular wave signal. In this configuration, even if the output voltage drops below the predetermined voltage, the output transistor is kept on in the period during which the output voltage is low, and accordingly the output voltage can rise quickly.
However, although the above-mentioned approach considers the case in which the output voltage drops significantly, it does not consider the case in which the triangular wave is not linear. Thus, a required pulse width signal cannot be generated in the case in which an error output signal is lower when the triangular wave is not linear.